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(R)
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
DESCRIPTION:
IDT54/74FCT841A/B/C
Integrated Device Technology, Inc.
FEATURES:
* Equivalent to AMD's Am29841-46 bipolar registers in pinout/function, speed and output drive over full temperature and voltage supply extremes * IDT54/74FCT841A equivalent to FASTTM speed * IDT54/74FCT841B 25% faster than FAST * IDT54/74FCT841C 40% faster than FAST * Buffered common latch enable, clear and preset inputs * IOL = 48mA (commercial) and 32mA (military) * Clamp diodes on all inputs for ringing suppression * CMOS power levels (1mW typ. static) * TTL input and output level compatible * CMOS output level compatible * Substantially lower input current levels than AMD's bipolar Am29800 series (5A max.) * Product available in Radiation Tolerant and Radiation Enhanced versions * Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT800 series is built using an advanced dual metal CMOS technology. The IDT54/74FCT840 series bus interface latches are designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/ data paths or buses carrying parity. The IDT54/74FCT841 is a buffered, 10-bit wide version of the popular `373 function. All of the IDT54/74FCT800 high-performance interface family are designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in the high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D0 PRE
DN
DP LE Q CLR CLR
DP LE Q CLR
LE
OE Y0 YN
2607 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1994 Integrated Device Technology, Inc.
APRIL 1994
DSC-4603/2
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IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22
P24-1 D24-1 E24-1 & SO24-2
21 20 19 18 17 16 15 14 13
DIP/CERPACK/SOIC TOP VIEW
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D8 D9 GND NC LE Y9 Y8
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 LE
INDEX
D2 D3 D4 NC D5 D6 D7
D1 D0 OE NC VCC Y0 Y1
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 3 2 1 28 27 26 25 24 23
L28-1
22 21 20 19
Y2 Y3 Y4 NC Y5 Y6 Y7
LCC TOP VIEW
2607 drw 03
PIN DESCRIPTION
FUNCTION TABLE(1)
InterOutputs YI Z Z Z Z L H NC H L H Z Z Function High Z High Z High Z Latched (High Z) Transparent Transparent Latched Preset Clear Preset Latched (High Z) Latched (High Z)
2607 tbl 02
CLR
DI LE
Name
I/O I
I I
Description When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. The latch data inputs. The latch enable input. The latches are transparent when LE is HIGH. Input data is latched on the HIGH-to-LOW transition. The 3-state latch outputs. The output enable control. When OE is LOW, the outputs are enabled. When OE is HIGH, the outputs (Y I) are in the high-impedance (off) state. Preset line. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR.
2607 tbl 01
CLR PRE OE
H H H H H H H H L L L H H H H H H H H L H L H L H H H H L L L L L L H H
Inputs LE X H H L H H L X X X L L DI X L H X L H X X X X X X
nal QI X L H NC L H NC H L H L H
YI
O I
OE PRE
I
NOTE: 1. H = HIGH, L = LOW, X = Don't Care, NC = No Change, Z = High Impedance
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IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating (2) Terminal Voltage VTERM with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature PT Power Dissipation IOUT DC Output Current Commercial -0.5 to +7.0 Military Unit -0.5 to +7.0 V
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance
(1)
Conditions VIN = 0V VOUT = 0V
Typ. 6 8
Max. 10 12
Unit pF pF
2607 tbl 04
-0.5 to VCC
-0.5 to VCC
V C C C W mA
0 to +70 -55 to +125 -55 to +125 0.5 120
-55 to +125 -65 to +135 -65 to +150 0.5 120
NOTE: 1. This parameter is measured at characterization but not tested.
NOTE: 2607 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L IOZH IOZL VIK IOS VOH Clamp Diode Voltage Short Circuit Current Output HIGH Voltage VCC = Min., IN = -18mA VCC = Max.(3) , VO = GND IOH = -300A IOH = -15mA MIL. IOH = -24mA COM'L. VOL Output LOW Voltage VCC = 3V, VIN = VLC or VHC, IOL = 300A VCC = Min. VIN = VIH or VIL IOL = 300A IOL = 32mA MIL. IOL = 48mA COM'L. VCC = 3V, VIN = VLC or VHC, IOH = -32A VCC = Min. VIN = VIH or VIL Parameter Input HIGH Level Input LOW Level Input HIGH Current Input LOW Current Off State (High Impedance) Output Current VCC = Max. Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC VI = 2.7V VI = 0.5V VI = GND VO = VCC VO = 2.7V VO = 0.5V VO = GND Min. 2.0 -- -- -- -- -- -- -- -- -- -- -75 VHC VHC 2.4 2.4 -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -- -- -- -0.7 -120 VCC VCC 4.3 4.3 GND GND 0.3 0.3 Max. -- 0.8 5 5(4) -5(4) -5 10 10(4) -10(4) -10 -1.2 -- -- -- -- -- VLC VLC(4) 0.5 0.5
2607 tbl 05
Unit V V
A
A
V mA V
V
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. This parameter is guaranteed but not tested. 7.22
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IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC - 0.2V
Symbol ICC ICC ICCD Parameter Quiescent Power Supply Current Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN VHC; V IN VLC VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = GND LE = VCC One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle OE = GND LE = VCC One Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle OE = GND LE = VCC Eight Bits Toggling Min. -- -- VIN VHC VIN VLC -- Typ.(2) 0.2 0.5 0.15 Max. 1.5 2.0 0.25 Unit mA mA mA/ MHz
IC
Total Power Supply Current (6)
VIN VHC VIN VLC (FCT) VIN = 3.4V VIN = GND VIN VHC VIN VLC (FCT) VIN = 3.4V VIN = GND
--
1.7
4.0
mA
--
2.0
5.0
--
3.2
6.5 (5)
--
5.2
14.5 (5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
2607 tbl 06
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IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841A Com'l. Symbol Parameter Propagation Delay DI to YI (LE = HIGH) Mil. FCT841B Com'l. Mil. FCT841C Com'l. Mil. Unit
Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
tPLH tPHL
CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 50pF RL = 500
1.5
9.0
1.5 10.0 1.5
6.5
1.5
7.5
1.5
5.5
1.5
6.3
ns
1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0 1.5 12.0 1.5 13.0 1.5 8.0 1.5 10.5 1.5 6.4 1.5 6.8 ns
tPLH tPHL
Propagation Delay LE to YI
1.5 16.0 1.5 20.0 1.5 15.5 1.5 18.0 1.5 15.0 1.5 16.0 1.5 12.0 1.5 14.0 1.5 8.0 1.5 10.0 1.5 7.0 9.0 9.0 9.0 1.5 9.0 ns ns
tPLH tPHL tPHL tPLH tPZH tPZL
Propagation Delay, PRE to YI Propagation Delay, CLR to YI Output Enable Time OE to YI
1.5 14.0 1.5 17.0 1.5 10.0 1.5 13.0 1.5 1.5 13.0 1.5 14.0 1.5 10.0 1.5 11.0 1.5 1.5 14.0 1.5 17.0 1.5 10.0 1.5 10.0 1.5
1.5 12.0 1.5 10.0 1.5 9.0 ns
tPHZ tPLZ
Output Disable Time OE to Y I
tSU tH tW tW tW tREM tREM
Data to LE Set-up Time Data to LE Hold Time LE Pulse Width (3) Pulse Width(3) HIGH
1.5 11.5 1.5 13.0 1.5 8.0 1.5 8.5 1.5 6.5 1.5 7.3 RL = 500 CL = 300pF(4) 1.5 23.0 1.5 25.0 1.5 14.0 1.5 15.0 1.5 12.0 1.5 13.0 RL = 500 CL = 5pF(4) 1.5 7.0 1.5 9.0 1.5 6.0 1.5 6.5 1.5 5.7 1.5 6.0 RL = 500 CL = 50pF 1.5 8.0 1.5 10.0 1.5 7.0 1.5 7.5 1.5 6.0 1.5 6.3 RL = 500 CL = 50pF 2.5 -- 2.5 -- 2.5 -- 2.5 -- 2.5 -- 2.5 -- RL = 500 2.5 4.0 5.0 4.0 4.0 3.0 -- -- -- -- -- -- 3.0 5.0 7.0 5.0 4.0 3.0 -- -- -- -- -- -- 2.5 4.0 4.0 4.0 4.0 3.0 -- -- -- -- -- -- 2.5 4.0 4.0 4.0 4.0 3.0 -- -- -- -- -- -- 2.5 4.0 4.0 4.0 4.0 3.0 -- -- -- -- -- -- 2.5 4.0 4.0 4.0 4.0 3.0 -- -- -- -- -- --
CL = 50pF
ns
ns ns ns ns ns ns ns
PRE LOW CLR Pulse Width(3) LOW Recovery Time PRE to LE Recovery Time CLR to LE
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. These parameters are guaranteed but not tested. 4. These conditions are guaranteed but not tested.
2607 tbl 07
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IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
DEFINITIONS: 2607 tbl 08 CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
tSU
tH
PROPAGATION DELAY
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 3.5V 1.5V tPHZ 0.3V VOH 0V
2607 drw 04
DISABLE 3V 1.5V 0V 3.5V 0.3V VOL
tPLZ
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
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IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
XXXX IDT XX FCT Temp. Range Device Type X Package X Process Blank B P D E L SO 841A 841B 841C 54 74 Commercial MIL-STD-883, Class B Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC 10-Bit Non-Inverting Latch
-55C to +125C 0C to +70C
2607 drw 05
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